Id. eures: 7229539, id. eures: soc staff architect
Barcelona
...DESIGN FOR ASIC OR FPGA. EXPERIENCE WITH ARCHITECTURE TRADE-OFFS AND DESIGN METHODOLOGIES FOR OPTIMAL PERFORMANCE POWER AREA COST (PPAC) IN ADVANCED TECHNOLOGIES.PROFICIENCY IN PERFORMANCE MODELLING, SIMULATION FRAMEWORKS AND SCRIPTING.STRONG KNOWLEDGE AND INDUSTRY EXPERTISE IN MULTIPLE ASPECTS OF SOC ARCHITECTURE DEFINITION [...]